Ghazi System on a Chip

An SoC (System on a Chip) design for Google-sponsored Open MPW shuttles for SKY130. The processor core is the 3-stage version of the Buraq Core RV32IMC. The hardware implementation incorporates options such as IRQ, Multiply, Divide, and the compressed (16 bit) ISA for embedded applications. The SoC has peripherals such as GPIO, UART, a platform level interrupt controller (PLIC) as well as a timer and a debug module all connected using the Tilelink Interconnect and is going to be fabricated using a 130nm process in collaboration with Efabless and SkyWater which will be funded by Google.

FEATURES:

• Support for M extension with a single cycle "Fast" multiplier
• Separate instruction and data memories
• TileLink Un-Cached Lightweight (TL-UL) Bus Protocol
• 32 GPIO with configurable interrupts and option for masked writing
• 2 pin full duplex UART • RISC-V compliant interrupt controller
• 64-bit timer with 12-bit prescaler and 8-bit step register
• JTAG Test Access Port (TAP) for debug