OpenLane is an automated RTL to GDSII flow for design exploration and optimization that uses OpenROAD, Yosys, Magic, Netgen, Fault, OpenPhySyn, CVC, SPEF-Extractor, CU-GR, Klayout, and custom methodology scripts. The flow covers the entire ASIC implementation process, from RTL to GDSII. Micro Electronics Research Lab conducting a workshop on OpenLane Tools in collaboration with the Open-Source FPGA Foundation and support of Paklaunch.com. This workshop is specifically aligned for Pakistani Engineering undergrad and graduate students and faculty who have an Electrical/Electronics background. It will enable you to design your own chip using the open-source tool "OpenLane" so that you can participate in Tapeout Pakistan. The workshop is entirely free of charge.