Looking for both fresh graduates and experienced people
Front End – RTL Design Engineer:
Familiarity with Computer Architecture.
Familiarity or experience in RTL design with Verilog and/or VHDL is required.
Familiarity with VLSI Design.
Familiarity with LINUX/UNIX OS.
Familiarity with scripting languages like python and/or perl.
Excellent Communication Skills.
Good command of written English and reading comprehension.
Front End – RTL Verification Engineer:
Familiarity or experience with RTL verification – Bus Functional Models (BFMs).
Familiarity with Computer Architecture.
Familiarity with VLSI Design.
Familiarity with LINUX/UNIX OS.
Familiarity with scripting languages like python and/or perl.
Excellent Communication Skills.
Good command of written English and reading comprehension.
Physical Design-APR Engineer:
Familiarity VLSI structural design methodologies and develop design flows.
Familiarity structural physical designs for, such as functional equivalency, timing/performance, noise, layout design rules, reliability and power.
Performs all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing.
Familiarity with APR tools from SNPS-ICCII or Cadence -Innovus.
Familiarity with LVS/DRC using Calibre.
Familiarity with LINUX/UNIX OS.
Familiarity with scripting languages like python, perl, and TCL.
Excellent Communication Skills.
Good command of written English and reading comprehension.
CMOS Mixed Signal Design Engineer:
Basics knowledge CMOS device physics.
Familiarity CMOS digital Circuit Design.
Familiarity with CMOS small signal modelling of analog ckts. Being able to figure out the output impedance (rout) and transconductance (gm, gain and phase margin.
Familiarity with basic analog structures: current mirrors, opamps, I/V ref, VCOs.
Familiarity with Cadence spectre and/or hspice for analog ckt simulations.
Familiarity with other circuit simulators a plus.
Familiarity with analog layout and Cadence Virtuouso.
Familiarity with LINUX/UNIX OS.
Familiarity with scripting languages like python, perl and TCL..
Excellent Communication Skills.
Good command of written English and reading comprehension.
FPGA Designer:
Some experience in one or more HDL language (System Verilog, Verilog), and one or more scripting language (TCL, Python, Perl, Shell-scripting.
Some experience with SoC design methodologies that involve multiple clock domains, clock power management and system debug.
Modeling: experience in C/C++/SystemC,
Preferably have some hands on experience with VIVADO and Xilinx FPGAs.
Preferably some networking protocol understanding.
Software Drivers:
Familiar with Linux kernel, IPC, and device driver model.
Familiar with various hardware elements of latest data center environment.
Familiar with embedded systems software stack.
Familiarity with OVS and PCIe drivers.
Some Understanding of DPDK/SRIOV protocol
Min 2-3 years Experience in C/C++.
About MERL
MERL is an equal opportunity employer does not discriminate based on race, ethnicity, color, religion, sex or social background.
MERL strives to provide an equitable work environment based on meritocracy, trust, respect and fairness.
Training would be provided in the area of deficiencies. Need commitment from potential candidates for 2-3yrs.
Competitive stipends/Salaries would be given matching the education and skill set as per offered in the local market.