LLVM Compiler

We are preparing to move forward after the tape-out of the SoCs. We aim to add another extension known as the Vector Extension (short:' V') to our core. This will accelerate our processing speed for complex machine algorithm. We hoped that a low-level virtual machine (LLVM) will provide the opportunity for us to write an inline vector extension assembly. We are forming a team that is solely exploring an LLVM. Another work that is in progress is the optimization of CHISEL generated Verilog which is generated by FIRRTL. Usually, the CHISEL generated Verilog is not much readable the naming convention is not understandable by the observer so for tackling this problem the subset of the students is working on that.