The team behind the RTL (Register Transfer Level), APR (Placement and Routing) and both Pre and Post Synthesis Verification of Ghazi System on a Chip. Uses of a core in deeply embedded systems such as IoT end-nodes range from simple control and interaction with peripherals, to the execution of light-weight processing, all the way up to the computation of complex signal processing algorithms. Design of such cores usually involves high royalty fee and copyright implications when using ARM or Intel x86 based architecture. Thus, an SoC, that uses a core based on an open source ISA (Instruction Set Architecture) is often required that we could easily adapt to suit multiple specifications as needed.

This team is working on the design of a complete System on a Chip (SoC) that is built from scratch based on the RISC-V Instruction Set Architecture (ISA). The Ibtida ابتدا project's aim is to build a completely open-source chip from scratch and take it from designing to fabrication using all open-source tools and Process Design Kit (PDK) made possible by Efabless, Google and FOSSI Foundation.

Azadi - آزادی means "The Freedom", this System on a Chip (SoC) is the start of many RISC-V based SoCs to come. It is the Final Year Project (FYP) of our MERL Research Interns i.e Zeeshan Rafique, Sajjad Ahmed, Muhammad Waleed Waseem and Usman Zain ul Abideen as a part of their Bachelor's Degree requirement. Azadi is an SoC with a 32-bit RISC-V signal core extended version of ibex we named it "buraq", it is a 3-stage pipeline core that implements the RV32IMFDC instruction set architecture, a limited number of peripherals UART, SPI, GPIO, PWM, and timer. It also contains a Software Development Kit (SDK) for rapid development, debugging and testing.