We are preparing to move forward after the tape-out of the SoCs. We aim to add another extension known as the Vector Extension (short:' V') to our core. This will accelerate our processing speed for complex machine algorithm. We hoped that a low-level virtual machine (LLVM) will provide the opportunity for us to write an inline vector extension assembly. We are forming a team that is solely exploring an LLVM. Another work that is in progress is the optimization of CHISEL generated Verilog which is generated by FIRRTL. Usually, the CHISEL generated Verilog is not much readable the naming convention is not understandable by the observer so for tackling this problem the subset of the students is working on that.

Rocket chip is the SoC generator written in Chisel and understood by quite a few. We make our own pedagogy which enabled our undergraduate students to understand this complex and powerful tool and its architecture which is not well documented and is a pain problem for many industries looking to adopt Chisel and RISC-V. Our goal is to Reverse Engineer the Rocket Chip generator by using the expertise of Scala (functional Programming and Object Oriented Programming).

The team behind the RTL (Register Transfer Level), APR (Placement and Routing) and both Pre and Post Synthesis Verification of Ghazi System on a Chip. Uses of a core in deeply embedded systems such as IoT end-nodes range from simple control and interaction with peripherals, to the execution of light-weight processing, all the way up to the computation of complex signal processing algorithms. Design of such cores usually involves high royalty fee and copyright implications when using ARM or Intel x86 based architecture. Thus, an SoC, that uses a core based on an open source ISA (Instruction Set Architecture) is often required that we could easily adapt to suit multiple specifications as needed.