Research Intern
An undergrad student, who is eager to learn and explore every diversity around her.
Projects
- RV32-I Single Cycle Processor Five stage pipelined Processor Verification of Azadi SoC
Interest
- Swarm Intelligence
- Artificial and Neural Networks
- Robotics
- Ethical Hacking
- Embedded systems
- RTL Design and Verification
Skills
- SystemVerilog
- SystemVerilog OOP
- System Verilog Randomization
- Universal Verification Methodology(UVM)
- RISC-V ISA
- RTL Design and Verification
- Cadence Xcelium
- Verilator
- Icarus Verilog
Contact