Syeda Rafia Fizza Naveed


Research Intern

This is Syeda Rafia Fizza Naveed, an undergraduate student of Computer Systems Engineering with a strong passion in the field Hardware Designing and Verification. Currently working as a research intern at MERL-UITU, I have gained valuable experience in tools like Vivado, Logisim, Proteus, MATLAB and many more. I have contributed to the hardware and verification team at MERL, showcasing my skills as an RTL designer. Alongside my hardware expertise, I possess proficiency in programming languages, microcontrollers, and AWS FPGA. With unwavering dedication, loyalty, and a commitment to continuous learning, I am eager to contribute my knowledge and enthusiasm to make a meaningful impact in the field.

Projects
  • RV32I Single Cycle Processor
  • 5 Stage Pipelining
  • NOVA1 SoC
  • Working on MultiCore SoC for SMP Linux
Interest
  • Hardware Designing and Verification
Skills
  • SystemVerilog
  • Verilog
  • AWS FPGA
  • RISCV Assembly Language
  • RISC ISA and Architecture
  • SoC (Custom SoC building and testing on amazon EC2 instance)
  • Advance Computer Architecture for Multicore
  • Git and GitHub
  • C++
  • Python
  • Leadership Skill
  • Team Management and Team Working Skills
  • Logisim
  • Proteus
  • MATLab
Contact