Projects
- RV32I Single Cycle Processor
- 5 Stage Pipelining
- Multi Core SoC for SMP Linux (Present)
- NOVA1 Project
- Compliance Testing Of Single Cycle
Interests
- hardware/Software design
- verification
- and FPGA emulation.
Skills
- RISCV Assembly Language
- UVM (Universal Verification Method).
- AWS-FPGA
- Arty a7-35t
- 100t Vivado.
- SystemVerilog
- Verilog
- C/C++
- Fusesoc
- Compliance testing and Formal verification.
- SoC (Custom SoC building and testing on amazon EC2 instance).
- RISCV Architecture
- Advance computer architecture for multicore
