I am an Engineering Educationist at UIT in Computer system department and associate with MERL-UIT as a ASIC Design Engineer.
Projects
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Interests
ASIC Design
DFT (Design For Testability)
Machine Learning
Skills
Familiar with industry standard CAD methodologies from Cadence (Genus
Innovus)
Familiar with open-source CAD methodologies e.g. Magic VLSI OpenLane Yosys etc
Work closely with RTL designers to debug and root-cause Physical Implementation issues related to design tools
etc
Deliver methodology and design flows for place & route STA formal equivalency power grid analysis and physical verification DRC/LVS across the design space
Implement Scan/Jtag/boundary scan insertion BIST and ATPG pattern generation
