OpenLane is an automated RTL to GDSII flow for design exploration and optimization that uses OpenROAD, Yosys, Magic, Netgen, Fault, OpenPhySyn, CVC, SPEF-Extractor, CU-GR, Klayout, and custom methodology scripts. The flow covers the entire ASIC implementation process, from RTL to GDSII. Micro Electronics Research Lab conducted a workshop on OpenLane Tools in collaboration with the Open-Source FPGA Foundation and support of Paklaunch.com. This workshop is specifically aligned for Pakistani Engineering undergraduate and graduate students and faculty who have an Electrical/Electronics background. It will enable you to design your own chip using the open-source tool "OpenLane" so that you can participate in Tapeout Pakistan. The workshop is entirely free of charge

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• Day 1: Introduction to APR, OpenLane, and Sky130 process design kit (PDK)
  
  

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• Day 2: Getting started with OpenLane and CMOS
  
  

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• Day 3: Register Transfer Level(RTL) Synthesis and Static Timing Analysis(STA)
  
  

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• Day 4: Floorplan+PDN
  
  

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• Day 5: Placement
  
  

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• Day 6: Clock Tree Synthesis(CTS)
  
  

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• Day 7: Routing
  
• Day 8: Final steps towards GDS