Our Research Interns Syeda Fizza Jaffery and Rehan Ejaz giving training to the MERL BATCH-4 students focused on RISC V Instruction Set Architecture Based processor designing. This course is all about how to design processor on drag and drop environment, which further extends to learning of Assembly Language, CHISEL (Constructing Hardware in a Scala Embedded Language), Functional Programming, System Verilog (Hardware descriptive language).

This training session was all about how to design processor on drag and drop environment which further extends to learning of assembly language and System verilog (Hardware descriptive language). after learning those the students are assigned a task to implement a basic Single cycle processor in CHISEL or System Verilog language.