Chip X A.I

Crafting the Future of Intelligent Hardware,

From Logic Gates to AI-Powered Systems


*Basic Module classes will begin from 9th December 2024.

Admissions

Open

Basic Module

Registration Deadline:
30th November 2024
Eligibility:
Any University Student
Duration
6 Months (3+3)
Location:
UIT University (MERL Lab)

Course Outline

BASIC MODULE

This Module is designed for making students familiar with the basics of Chip Designing on Both Software and Hardware Streams. It will be focused on building basics and explore the domain expansion on Software and Hardware co-domains in the Chip Designing Ecosystem.

MODULE 01

CHIP DESIGNING BASIC CONCEPTS

MODULE 01

CHIP DESIGNING BASIC CONCEPTS
Digital Logic Designing
This segment will provide students with a strong foundation in Digital Logic Design, equipping them with the essential skills to construct and analyze logical circuits. Students will learn fundamental concepts like Boolean algebra, logic gates, and combinational/sequential circuits, while developing critical logic-building skills.
RISC-V Instruction Set Architecture
In this segment, students will dive deep into the RISC-V Instruction Set Architecture (ISA). They will explore how a processor interprets and decodes machine code, breaking down each instruction to understand the role of every bit.
RISC-V Assembly Language
In this segment, students will engage with the fundamentals of assembly programming for the RISC-V ISA. They will work directly with machine code, writing assembly instructions to implement various programs such as generating the Fibonacci series, calculating multiplication tables, and more. Students will also learn to monitor and debug their code by closely examining CPU registers and main memory during execution.
Computer Architecture and Organization
In this segment, students will explore the inner workings of a CPU and gain a comprehensive understanding of how a processor functions. They will learn about key stages in the execution of tasks, including instruction fetch, decode, execution, memory access, and write-back. The course will cover essential concepts such as pipelining, control units, data paths, and cache memory.
Single Cycle CPU Designing
In this segment, students will learn how to design a single-cycle processor based on the RISC-V ISA. Instead of coding, the focus will be on building the processor at a low level using Digital Logic Design (DLD) principles. Students will implement their designs using a GUI-based drag-and-drop software called Logisim, allowing them to visually construct and simulate the processor's logic.
Five Stage Pipelined CPU
In this segment, students will be introduced to the concepts of pipelining and will learn how modern CPUs achieve hardware-level parallelism. They will explore how processors can execute multiple instructions simultaneously by breaking tasks into smaller stages, significantly improving performance. Students will understand the principles behind instruction-level parallelism (ILP) and how CPUs are able to perform a large number of tasks natively, enhancing efficiency.

MODULE 02-A

SOFTWARE ORIENTED CHIP DESIGNING

MODULE 02-A

SOFTWARE ORIENTED CHIP DESIGNING
Object Oriented Programming
In this segment, students will be introduced to the core concepts of Object-Oriented Programming (OOP). They will learn how to create classes, define objects, and explore key OOP principles such as inheritance, polymorphism, encapsulation, and abstraction.
Introduction to Scala and CHISEL
In this segment, students will be introduced to the basics of the Scala programming language, focusing on its syntax, functional programming concepts, and object-oriented features. They will also be introduced to the Constructing Hardware in Scala Embedded Language (CHISEL), a powerful hardware construction library. Students will learn how Scala is used to describe hardware designs, enabling them to construct complex digital circuits with a high-level programming approach.
Functional Programming in Scala
In this segment, students will dive into the functional programming paradigm of Scala, exploring how powerful logic can be implemented with minimal lines of code. They will learn how functional programming concepts like higher-order functions, zipping, and immutability can be leveraged to create concise and efficient code
Single Cycle Core in CHISEL
In this segment, students will learn how to design and implement a RISC-V based single-cycle CPU using the CHISEL hardware description language (HDL). They will apply both Object-Oriented and Functional Programming approaches to efficiently structure and manage their design. Through CHISEL, students will explore how to build modular, scalable hardware components while leveraging high-level programming techniques to simplify the design process.
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MODULE 02-B

HARDWARE ORIENTED CHIP DESIGNING

MODULE 02-B

HARDWARE ORIENTED CHIP DESIGNING
SystemVerilog Basics
Students learn the basics of SystemVerilog, including data types, operators, and expressions, which are essential for RTL (Register Transfer Level) design. This topic covers both structural and behavioral modeling.
Combinational Circuit Design
Students explore combinational logic design in SystemVerilog, creating circuits that perform arithmetic and logical operations. This topic helps them understand the difference between combinational and sequential logic.
Sequential Circuit Design
This section focuses on sequential logic, including flip-flops and state machines. Students learn to design circuits that depend on previous states, such as counters and shift registers.
Testbench and Verification
Students are introduced to testbench design, learning to write SystemVerilog code that validates the functionality of their hardware. This includes understanding verification principles and techniques for digital circuits.
Synthesis Concepts
This topic covers the synthesis process, where RTL code is transformed into gate-level representations. Students learn about constraints and optimization during synthesis, essential for turning designs into physical hardware.
Timing Analysis
This section introduces timing analysis, where students learn to check for timing violations and ensure that circuits meet performance requirements. This topic is crucial for achieving reliable and efficient designs.

Course Outline 2A

ADVANCE MODULE 01

EMBEDDED SOFTWARE ENGINEERING MODULE

MODULE

Embedded Software Engineering

MODULE

Embedded Software Engineering
SoC Firmware Development
Students learn to write bootloaders and firmware for System-on-Chips (SoCs), focusing on hardware initialization and low-level programming. This topic covers hardware abstraction layers and managing peripheral devices.
Interrupts and Exception Handling
This section teaches students to handle interrupts and exceptions, which are critical for real-time response in embedded systems. They learn techniques to prioritize and manage multiple interrupt sources.
Real-Time Operating Systems (RTOS) Basics
Students are introduced to RTOS principles, including task scheduling, inter-task communication, and synchronization mechanisms. This is essential for applications requiring time-sensitive operations.
RTOS Porting
In this topic, students learn to port an RTOS onto embedded platforms, configuring it to manage hardware resources and execute real-time tasks efficiently.
Linux Kernel Porting
Students gain experience in porting the Linux kernel for embedded devices, learning kernel configuration, compilation, and customization. This topic also includes device driver development for peripheral interfaces.
Embedded Application Development
This section focuses on application development for embedded systems, teaching students to use low-level libraries and APIs for efficient hardware interaction.

ADVANCE MODULE 02

RTL With Artificial Intelligence

MODULE

RTL with Artificial Intelligence

MODULE

RTL with Artificial Intelligence
Machine Learning Basics
Students are introduced to machine learning concepts, covering neural networks, deep learning, and foundational AI algorithms. This section provides an overview of supervised and unsupervised learning techniques.
Hardware for AI
This topic focuses on designing efficient hardware to support AI workloads. Students explore custom architectures for running neural networks and optimizing machine learning models on hardware.
FPGA Acceleration for AI
Students learn to use FPGAs to accelerate AI applications, focusing on how to map neural network operations onto programmable hardware for high performance.
ASIC Design for AI
This section covers designing application-specific integrated circuits (ASICs) for AI, providing insights into creating custom hardware for specific AI tasks like image recognition and natural language processing.
Optimization of AI Workloads
Students learn techniques for optimizing AI workloads for real-time and resource-constrained environments, ensuring that models run efficiently on embedded platforms.
Deployment of AI Models
This topic teaches students how to deploy machine learning models on embedded and edge devices, addressing challenges like latency, power consumption, and memory usage.

Course Outline 2B

Advance module

This Module is designed for 2B group students

MODULE

Advanced Chip Designing

MODULE

Advanced Chip Designing
System-on-Chip (SoC) Architecture
This topic provides an overview of SoC design, including core elements like CPU, memory, and peripheral interconnections. Students learn the principles of integrating various subsystems within a single chip.
Network-on-Chip (NoC) Design
Students explore NoC architectures for efficient communication within SoCs, learning about topologies, routing protocols, and optimization techniques for data transfer.
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High-Performance Computing Accelerators
This section introduces students to accelerator design, including GPUs and custom ASICs, for applications like scientific computing and artificial intelligence.
Memory Subsystems
Students learn about memory subsystem design, including caches and memory controllers, which are critical for achieving high-speed data access in SoCs.
Interfacing IP Cores
This topic focuses on integrating third-party IP cores into SoCs, teaching students about IP standards and interoperability challenges in chip design.
Power and Thermal Management
Students learn techniques to manage power consumption and thermal dissipation, which are essential for reliable operation and energy-efficient designs in modern chips.

MODULE

RTL Verification

MODULE

RTL Verification
SystemVerilog for Verification
This topic covers the basics of SystemVerilog for verification, focusing on test case creation and simulation. Students learn to write assertions and create testbenches for verifying digital designs.
Python for Verification
Students learn to use Python in verification workflows, exploring how scripting languages can aid in automating test setups and analyzing simulation results.
Formal Verification
This section introduces formal verification methods, where students learn to mathematically prove the correctness of designs using tools to check properties and verify constraints.
Verification of RISC-V Designs
Students gain hands-on experience in verifying RISC-V cores, focusing on compliance testing to ensure that designs adhere to the RISC-V standard.
Universal Verification Methodology (UVM)
This topic introduces UVM, an industry-standard methodology for creating reusable, scalable testbenches. Students learn object-oriented verification techniques and testbench structure.
Coverage and Conformance Testing
This section covers coverage metrics and conformance testing, teaching students how to evaluate test completeness and ensure that all design features are verified.